I am running into an error on Vivado. I am trying to run implementation to program my Basys board, but I am running into the following error:
[DRC MDRV-1] Multiple Driver Nets: Net ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/nextS[1] has multiple drivers: ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/Q_i_3/O, and ScrlFSM/RLC2B/DER1/DFF_R1/DFF1/Q_i_2/O.
This is my VHDL for my top level:
architecture Structural of xxxxxxxxxxx is
component WordTo4DigitDisplayDriver is
port (
WORD : in STD_LOGIC_VECTOR(15 downto 0);
PULSE : in STD_LOGIC;
CLK : in STD_LOGIC;
SEGMENT : out STD_LOGIC_VECTOR(0 to 6);
ANODE : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
component PulseGenerator_1ms is
port (
CLK : in STD_LOGIC;
PULSE : out STD_LOGIC
);
end component;
signal pulse_1ms : STD_LOGIC;
component ScrollFSM is
port (
L : in STD_LOGIC;
R : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
DISPLAY : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
begin
Wt4DDD: WordTo4DigitDisplayDriver
port map (
WORD => SWITCH(15 downto 0),
PULSE => pulse_1ms,
CLK => CLK,
SEGMENT => SEGMENT,
ANODE => ANODE
);
PulseGen: PulseGenerator_1ms
port map (
CLK => CLK,
PULSE => pulse_1ms
);
ScrlFSM: ScrollFSM
port map (
L => BTNL,
R => BTNR,
CLK => CLK,
RESET => BTND,
DISPLAY (1 downto 0) => LED(15 downto 14)
);
end architecture;
My code for ScrollFSM:
architecture Structural of ScrollFSM is
component Reg_LOAD_CLR_2bit is
port (
D : in STD_LOGIC_VECTOR(1 downto 0);
CLK : in STD_LOGIC;
LOAD : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
signal currentS : STD_LOGIC_VECTOR(1 downto 0);
signal nextS : STD_LOGIC_VECTOR(1 downto 0);
alias NS1 : STD_LOGIC is nextS(1);
alias NS0 : STD_LOGIC is nextS(0);
alias S1 : STD_LOGIC is currentS(1);
alias S0 : STD_LOGIC is currentS(0);
begin
NS1 <= (not S1 and not S0 and L) or (S1 and S0 and L) or (not S1 and S0 and R) or (S1 and not L and not R) or (S1 and not S0 and not L and not R);
NS1 <= (S0 and not L and not R) or (not S0 and L and not R) or (not S0 and not L and R);
RLC2B: Reg_LOAD_CLR_2bit
port map (
D => nextS,
CLK => CLK,
LOAD => '1',
CLR => RESET,
Q => currentS
);
DISPLAY <= currentS;
My code for DFF1:
architecture Behavioral of DFF is
begin
process (CLK)
begin
if rising_edge(CLK) then
Q <= D;
end if;
end process;
end architecture;
I read through possible causes of this, and it seems like I am tying multiple outputs together. I cannot find any case of that in my top level, so I'm not sure what the issue is. I tried resolving any possible errors in both my top level and in the rest of my VHDL but am still getting the same error.
The multiple drivers are in the ScrollFSM module, here
NS1 <= (not S1 and not S0 and L) or (S1 and S0 and L) or (not S1 and S0 and R) or (S1 and not L and not R) or (S1 and not S0 and not L and not R);
NS1 <= (S0 and not L and not R) or (not S0 and L and not R) or (not S0 and not L and R);
These are both concurrent assignments; they are not executed sequentially.
Maybe one of them should be NS0 <= ...