SystemVerilog When instantiating a module how can I connect an output to each wire of a multidimensional bus

Say I have the multidimensional bus

wire logic [7:0]example_bus[60] [16][4];

and a module has the output

output logic [7:0]example_out[16][4];

How would I assign example_out to all 60 wires in example_bus?

I know how to assign it to individual wires.

example_mod example_mod1(
.example_out(example_bus[0]));

But I can't work out how to assign the output to the whole bus.

I have considered using a seperate assignment but I find that usually causes timing problems.

You can use an assigment pattern to make the assigments simpler

  wire logic [7:0] example_bus[60] [16][4];
  wire logic [7:0] example_temp [16][4];
  
  example_mod example_mod1(
    .example_out(example_temp)
                  );
  assign example_bus = '{default:example_temp};

But that won't change the fact that each wire of example_out fans out to 60 wires in example_bus. It is effectively the same as

for(genvar i=0;i<60;i++) begin
        assign example_bus[i] = example_temp;
end