How to access a slice with a dynamic value in SystemVerilog?

I want to access a slice with a dynamic value. I have tried to do it in different ways. In the first case reducing the logic of the module for the control of the index value etc, verilator told me that it is not a constant value and I agree with that and then I change for the second version but I got the same result.

1:

module m1 (
input  logic [4:0] in1,  // 8-bit input vector 1
input  logic [4:0] in2,  // 8-bit index
output logic [4:0] out   // 8-bit output vector
);
logic add;

always_comb begin
add = (in2[in1[4:0]-1] & (in2[(in1[4:0]-2):0] != '0); //summary rounding
end

out = in1 + add;//summary of the final operation
endmodule

2:

module m1 (
input  logic [4:0] in1,  // 8-bit input vector 1
input  logic [4:0] in2,  // 8-bit index
output logic [4:0] out   // 8-bit output vector
);
logic add;

always_comb begin
for (int i = 0; i < 4; i++) begin
if((in1[4:0]-2) == i)begin
add = (in2[in1[4:0]-1] & (in2[(i:0] != '0); //summary rounding
end
end

out = in1 + add;//summary of the final operation
endmodule

The logic I am trying to implement is the rounding mode of riscv-v 1.0.

I have tried several tests trying to do static logic but I can't find a way to solve the problem. How can I implement this logic in hardware.

Good afternoon,

The final solution that I found is the next one:

prev_shift = '0;
prev_shift = in2 << (in1[range in2] - 2);
not_zero = prev_shift != 0;

Thank @Suhas for the help