verilogsystem-verilog

String triple quotes not getting accepted by simulators


Triple-quoted strings are supported as per IEEE 1800-2023 LRM, but none of the simulators are able to compile (getting the below error). Any lead will help me to understand it better.

module top;
  
string foo;

  initial begin
  foo =  """
This is one continuous string.
Single ' and double " can
be placed throughout, and
only a triple quote will end it.
""";
    $display("%0s",foo);
  end
endmodule

Getting unterminated string error

https://edaplayground.com/x/Rj4A


Solution

  • The IEEE 1800-2023 LRM was just published in March 2024. Although some "new" features have been supported by tools for a number of years already, others will take a number of years to implement. Some tools have yet to support all of 1800-2005.