I'm a junior Electronic Engineering student currently learning Verilog. I've been studying various modeling methods in Verilog, including Structural, Dataflow, and Behavioral modeling. I have a question regarding the conversion of Behavioral modeling to Structural modeling:

Does Verilog automatically convert Behavioral modeling into Structural modeling during synthesis, or do I need to convert the code manually?

I've found a helpful answer on how to convert Behavioral modeling into Structural modeling in Verilog here: Verilog Behavioral (RTL) to Structural. verilog behavioral RTL to structural

However, my main concern is whether this conversion needs to be done manually by me, or if the synthesis tools handle it automatically.

So far, I've written model and testbench code for FSMs, synchronous and asynchronous counters, and registers using Behavioral modeling. My questions might stem from my current level of understanding.

Any insights or resources on how to approach this conversion process and better understand hardware realization would be greatly appreciated.

Logic synthesis:

In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool.

Yes, a synthesis tool reads in the behavioral Verilog code (known as RTL), and outputs a Verilog structural model (also known as a gate-level netlist), when configured to do so.

Refer to the documentation for your specific synthesis tool for more details.