How can I declare an output of a module to be a decimal number instead of a single bit?

I want to write a simple random decimal number generator from an arbitrary range.

I wrote the following code in Verilog:

module randnumgen (clock, r);
input clock;
integer n;
output r;
always @(posedge clock) begin
    n <= 0 + {$urandom} % (10 - 0) ;
end
assign r = n;
endmodule

And testbench:

`timescale 1ns / 1ps
module randnumgen_tb; 
// Inputs
reg clock;
// Outputs
wire r;
// Instantiate the Unit Under Test (UUT)
randnumgen uut (.clock,.r);
initial begin
// Initialize Inputs
clock  = 1'b1;
end
always #1 clock = ~clock;  
endmodule

Unfortunately, the result (output r) still behaves like a binary number. It seems to me that I entered the data type incorrectly somewhere (wire, integer, etc.). Help me correct the error, please.

You have only declared r as a 1-bit wide signal in both the top-level tb and randnumgen. Change to this style of port declarations:

module randnumgen (input clock, output int r);
  int n;
...
endmodule
module randnumgen_tb; 
// Inputs
logic clock;
// Outputs
int r;

Make sure all your files have a .sv extension. Also, you should use $urandom_range(maxval,minval) to generate a random number within a range.