I'm working in Intel Quartus Prime Lite 23.1 with a template project for the Arduino MKR Vidor 4000. Specifically, it uses the Cyclone 10 LP 10CL016YU256C8G.
Right now I'm trying to write a module that, for now, simply reroutes some wires to a set of ports connected to LEDs for debugging. Right now the only data being sent is the MSB of a 32-bit clock.
The problematic module TestLeds is defined along with the top level module entity MKRVIDOR4000_top like so:
module TestLeds(
inout wire [6:0] bMKR_A,
inout wire [14:0] bMKR_D,
inout wire [7:0] bByte
);
assign bByte = '{bMKR_A[5], bMKR_A[6], bMKR_D[0], bMKR_D[1], bMKR_D[2], bMKR_D[3], bMKR_D[4], bMKR_D[5]};
endmodule
module MKRVIDOR4000_top
(
// system signals
input iCLK,
// SAM D21 PINS
inout [6:0] bMKR_A,
inout [14:0] bMKR_D
);
reg [5:0] rRESETCNT;
reg [31:0] hadcounter;
always @(posedge iCLK) begin
if (!rRESETCNT[5]) begin
rRESETCNT <= rRESETCNT+1;
hadcounter <= 0;
end else begin
hadcounter <= hadcounter + 1;
end
end
wire [7:0]bMKR_LED;
TestLeds leds(
.bMKR_A(bMKR_A),
.bMKR_D(bMKR_D),
.bByte(bMKR_LED));
assign bMKR_LED[7:0] = hadcounter[31:31-7];
endmodule
This is a trimmed down and hopefully equivalent version of what I'm actually using, based on the template above.
It's in my understanding that the wire definitions should update the specific bMKR_A and bMKR_D ports by the direct connection to the hadcounter "register", but all of this seems to be ignored. That is, Quartus claims no gates for the compilation. I get the error Warning (12158): Entity "TestLeds" contains only dangling pins but do not understand how this happens or how to solve it.
I have tried simulating this project as well but Quartus does not allow me to select any language and I cannot find how else to do this task.
To be more specific about what I'm here for:
The problem is that the design has no outputs.
It looks like variable bMKR_D is intended to be an output but its not driven anywhere in the design.
One thing causing the confusion is that you are using mode inout for your ports. There is no reason to use that for the code you have. Use input or output. Walk thru your design and make the changes; it will not take long to realize that you have no outputs. Clarify for yourself what you intend the outputs to be at the module level and the top level. Hand sketch it if you need to. Don't use mode inout
With no outputs ('bMKR_D' is undriven), synthesis will remove the entire design. One job of synthesis is to remove unused logic, and with no outputs its all unused.
Mode 'inout' ports are used to infer tri-state drivers, you don't have them here.
You don't need Quartus to simulate this small design. www.edaplayground.com is free and works well for small designs with a couple of files. Register with an institutional email and you can run near full versions of all the industry standard simulation tools, with a couple of cut and paste then a big run button.
There are other problems with your code. FPGA designs which use flip-flops usually have a reset input to reset the flops on power up. In simulation the reset is usually asserted at t=0 for some number of clocks and released. Without a reset the flops have no initial value (actually its x in simulation) and adding one to them is still x. I would search on Verilog synchronous counter. You can take a look at Wikipedia counter or find your own. Either way I suggest you add a reset to your design, and use it to initialize a standard synchronous counter.