vhdl

VHDL if statement precedence

So, this code was given to me to fix, and it made me wonder how it actually should work. The key pitfall here is multiple IF statements in a process that sets/clears the same output. So which one "wins"?

Example:

IF(A = 0) THEN
  C <= '0';
END IF;

IF (B = 2) THEN
 C <= '1';
END IF;

Edit: fixed wrong output name.

So what will happen if A is 0 and B is 2 ??? Will the last IF take precedence?? And where in the VHDL spec is this precedence defined ?

The simulator showed that the first one wins, but I'm not sure it is correct

Solution

  • VHDL LRM 11.3, Process statement defines:

    "A process statement defines an independent sequential process representing the behavior of some portion of the design"

    with:

    process_statement_part ::=
 { sequential_statement }

...

sequential_statement ::= [§ 10.1]
 wait_statement
 | assertion_statement
 | report_statement
 | signal_assignment_statement
 | variable_assignment_statement
 | procedure_call_statement
 | if_statement
 | case_statement
 | loop_statement
 | next_statement
 | exit_statement
 | return_statement
 | null_statement

    so all statements in a process are sequential. A process will either execute once when a signal in the sensitivity list has a 'event or the process will execute as a loop until it hits a wait statement. All code executed within this period occurs within the same delta cycle, and hence if multiple assignments to a signal occur, the last one is the one that will be scheduled to be assigned at the end of the delta cycle, as it will override all previous assignments.

    VHDL LRM 10.5.2.2 Executing simple assignment statement (under 10.5 Signal Assignment Statements):

    The sequence of transactions is then used to update the projected output waveform representing the current and future values of the driver associated with the simple waveform assignment statement. Updating a projected output waveform consists of the deletion of zero or more previously computed transactions (called old transactions) from the projected output waveform and the addition of the new transactions, as follows:

    a) All old transactions that are projected to occur at or after the time at which the earliest new transaction is projected to occur are deleted from the projected output waveform.

    b) The new transactions are then appended to the projected output waveform in the order of their projected occurrence.

    So in your case, assuming the code you posted is executed in the same delta cycle, with A=0 and B=2, then b will end up being '1'. If this is not the case, then:

    1. Some form of user error, either with the code posted or reading the waveform
    2. The Simulator has a bug.

    I highly doubt 2 is the case as this is pretty fundamental mechanism of VHDL that has been like this since VHDL 1987. If you still are still not seeing this, then I suggest you post a complete MCVE so that we can diagnose what the problem is.