Why immediate[0] is set to zero for jump and link instruction in riscv architecture? What is the main purpose do do that?
I am not sure of whether the JAL is a PC relative instruction and even if it is why the imm[0] is set to zero?
Perhaps you're confusing the nomenclature. There is:
For (1.) the value to encode into the immediate will always have the LSB as zero, i.e. will always be even, so that last zero bit is not put into the encoding, allowing more bits for range.
For (2.) the processer extracts the decoded immediate by
rearranging the (scrambled) bits, and,
appending the missing zero, and finally,
sign extending the value to full word size (32 or 64 bits depending on arch)
(These are the things done, though most likely in parallel rather than as individual and/or sequential steps.)
For (3.) the processor will add the pc to compute the effective address, that effective address becomes the new pc. Thus, this instruction is considered a pc-relative branch.
I am not sure of whether the JAL is a PC relative instruction
Yes, it is pc-relative instruction because in usage the decoded immediate is added to the pc to produce the effective address used as the branch target, i.e. the pc is set to pc + decoded immediate value.
even if it is why the imm[0] is set to zero?
It is not that it is set to zero, rather it is known to be zero, so in some cases, such as with jal that zero last bit is not encoded — thus, that last bit, known to be zero, is e reproduced/reintroduced in the decoded immediate.
An instruction address must be even, by definition of the architecture and instruction set. Regardless of instruction width, an instruction stream may not start on an odd byte (address) boundary and this is mandated by the architecture. However, sensible instruction widths are chosen so this works well.
Instructions are at least 2 bytes wide and otherwise multiples of 2 bytes. The regular instruction set defines 32 bit aka 4 byte wide instructions, while the compressed instruction extension adds 16 bit aka 2 byte wide instructions. The instruction set allows for addition extensions to define 48 bit / 6 byte wide and 64 bit / 8 byte and even wider — though no extensions define instructions of these larger sizes as yet.
Since an instruction address must be even (by definition), it will always have an LSB of value 0. Further, the difference between any two instruction addresses (such as is needed for pc-relative branches) is also know to be even (as even - even = even), and thus, such a difference can be and is encoded without that LSB (whose value is known to be 0).