Modeling a D-type Flip Flop in Verilog with gate-level modeling vs. behavioral modeling seems to result in state transitions happening at different edges of the clock signal. I'm sure I'm missing something, so looking for some guidance. With a gate-level model, there are two internal D Latches (at least the way I'm doing it) with the second (output) latch having an inverted clock signal. On the positive edge, the first latch picks up the input, and on the negative edge the second latch propagates the input to the output. With a behavioral model (triggering on posedge) the output of the latch seems to transition instantly on the positive edge. These seem to be two very different outcomes. This is when doing simulation via iverilog or Vivado.
The CPU works fine with either behavioral or gate-level modeling, but the transitions happen on different phases of the clock signal.
Behavioral, transitions happen on positive edge
reg [15:0] R;
assign OUT = R;
initial R = 0;
always@(posedge CLK) begin
if(ST) begin
R <= X;
end
end
Gate-Level, transitions happen on the negative edge
If I update the behavioral Verilog to trigger on the negative edge, my application (a CPU) fails.
Question is: does this matter? Is there a better way to do a behavioral model of a D-type flip flop that more closely matches a gate-level implementation? Or, if you do simulation after synthesis does this difference go away? Thanks in advance!
Update: part of my confusion here is between a regular DFF and a DFF in master slave configuration. I don't think I require a master/slave setup for my registers. The behavior model captures a regular DFF and works fine for my purposes. I appreciate the responses which have helped me sort this out!
I think your basic problem is here:
On the positive edge, the first latch picks up the input, and on the negative edge the second latch propagates the input to the output.
If you want a master-slave latch combination to look like a positive-edge-triggered D-type F/F, then the master should be transparent when the clock is low, with the slave capturing the master's state when the clock rises. On your schematic, N2 and N3 invert when CLK (and STO) are high. IOW, your master latch is transparent when CLK is hi, not lo. You'll probably fix it by changing AND_0 to a NAND.
But... don't bother. This is the wrong way to go about any sort of modelling. Back in the day, F/Fs were built as proper gate-level async circuits, where the feedback ensured that a [rising] edge on one input gave a stable sampled output. Nowadays, it's probably just a looped pair of inverters of some sort. I'm not aware of any real commercial circuits that ever implemented F/Fs as a pair of latches. The point is that you've actually got very little idea of what the real implementation is; that's the job of the (essentially analog) silicon people. For behavioural modelling, just use the normal always@(posedge CLK) code. For timing simulation, look at the source of your vendor's "gate level" model, and you'll almost certainly see that it's implemented behaviourally, as a truth table, with real delays back-annotated in.
