verilogquestasim

How to compile and run a single verilog file with Questa?

How to compile and run a single verilog/systemverilog file with Questa simulator?

Edit (some background and initial attempts):

During hardware development, the verilog source code can be compiled and run as any other software code. In this case using the Questa suite (see https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/)

What is the command sequence to compile and run a .v or .sv file with Questa suite? I tried just running vsim my_module.v but that was not enough.

Solution

  • To compile your Verilog file, use:

    vlog file.v

    Then, run the simulation with Questa using:

    vsim your_module