Why set "MCR p15, 0, %0, c9, c12, 1\t\n" :: "r"(0x80000000" in arm for enable performance counter?

I have raspberrypi 4, and I want to know how much cycles my code needs. I refer to this link article to implement the function I wanted. Although I have newer version raspberrypi, it has same architecture armv8 as raspberrypi 3. Luckily, it work for me.

But I have no idea why it needs to set up following code. To be more precise, I don't know why we need to set 0x80000000.

asm volatile ("MCR p15, 0, %0, c9, c12, 1\t\n" :: "r"(0x80000000));

I'm studying on Arm developer site, following image, I find c9 c12 is in red field following image. I'm trying to understand why we need to set 0x80000000. Is there datasheet provides more details on this? Thanks

The manual that you're looking for to find this information is the Arm Architecture Reference Manual for A-profile architecture. On the page you linked to, the table heading refers to a document particular to ARMv8-A. While I can't find an official Arm source for a document by that name, the Arm Architecture Reference Manual for A-profile architecture seems to provide that information/have taken its place. You can download the document from Arm Architecture Reference Manual for A-profile architecture.

That PMCNTENSET, Performance Monitors Count Enable Set register (for AArch32 operation) is described (for document version K.a) in subsection G8.4.8. The value 0x80000000 has all bits cleared, except the top bit (31), which is set. From the field description in the manual, this is the field C, bit [31], which has the description:

PMCCNTR enable. On writes, allows software to enable PMCCNTR. On reads, returns the PMCCNTR enable status.
0b0 PMCCNTR disabled.
0b1 PMCCNTR enabled.

The other bits are similarly defined to enable the PMEVCNTR<n>, but those are disabled here.

So the effect of this instruction is to enable PMCCNTR, Performance Monitors Cycle Count Register and disable the 31 PMEVCNTR<n>, Performance Monitors Event Count Registers, n = 0 - 30.