verilogsystem-verilogquartus

Array of wire OR-reduction is wrong

I tried to perform OR reduce operation on array. When on the left hand of assignment is an array of register, it's all right. When on the left side of assignment is an array of wire, then only the last element of array was involved into reduction. Why? How to correctly reduce arrays of wire?

This is a code that can help you understand this problem:

module tst_reduction;

parameter DATA_WIDTH = 3;
parameter SIZE = 4;
reg  [DATA_WIDTH-1:0] m  [SIZE-1:0];
wire [DATA_WIDTH-1:0] m1 [SIZE-1:0];
wire [DATA_WIDTH-1:0] out1;
wire [DATA_WIDTH-1:0] out2;

assign m1 = m;
assign out1 = m.or();  // m is a reg, all right
assign out2 = m1.or(); // m1 is a wire, problem

integer i, j;
initial begin
    m = {0, 0, 0, 0};   
    for (i = 0; i < SIZE; i = i + 1) begin
        for (j = 0; j < 2**DATA_WIDTH; j = j + 1) begin
            #10;
            m[i] = j;
        end;
        #10;
        m[i] = 0;
    end
    #10;
end

endmodule

I expect that out1 and out2 would be equal, but they are not.

The simulation output waveform of this example:

Simulation waveform

Solution

  • When I run your code on the Cadence simulator, out1 and out2 are equal to each other.

    waves

    When I run it on the Synopsys simulator, I get compile errors like:

    Error-[SV-FNYI] Feature not yet implemented
  SystemVerilog feature not yet implemented. Array manipulation method as the 
  RHS of a continuous assignment. Expression: m.or

    Perhaps Quartus has not implemented this feature properly. Report this to their support.

    Try your code on different simulators on EDA Playground.