Vectors multiplication

I know that if I want multiplication two types i have to put them to signed/unsigned, but what if I want multiplay concrete two vectors? This is what I have :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
architecture Behavioral of koder is
signal g0 : std_logic_vector(2 downto 0) := "111";
signal g1 : std_logic_vector(2 downto 0) := "101";
signal bits : std_logic_vector (15 downto 0) := "0000111100001111";
signal p0 : std_logic_vector(1 downto 0) := "00";
signal MSG : std_logic_vector(32 downto 0); 
signal msg1 : std_logic_vector;
signal msg2 : std_logic_vector;

process(CLK)
variable result_g0: std_logic_vector(2 downto 0);  -- Temporary result
variable result_g1: std_logic_vector(2 downto 0);  -- Temporary result
variable msg1 : std_logic;  
variable msg2 : std_logic;
variable msg3 : std_logic;
variable msg4 : std_logic;
variable msg5 : std_logic;
variable msg6 : std_logic;
begin   
    if rising_edge(CLK) then
        case state is
            when K0 =>
                result_g0(0) := (g0(0) and p0(0));
                result_g0(1) := (g0(1) and p0(1));
                result_g0(2) := (g0(2) and bits(0));
                msg1 := result_g0(0) xor result_g0(1) xor result_g0(2);  --mod2
                
                result_g1(0) := (g1(0) and p0(0));
                result_g1(1) := (g1(1) and p0(1));
                result_g1(2) := (g1(2) and bits(0));
                msg2 := result_g1(0) xor result_g1(1) xor result_g1(2);  --mod2
     
            when K1 =>
                result_g0(0) := (g0(0) and p0(1));
                result_g0(1) := (g0(1) and bits(0));
                result_g0(2) := (g0(2) and bits(1));
                msg3 := result_g0(0) xor result_g0(1) xor result_g0(2);  --mod2
                
                result_g1(0) := (g1(0) and p0(1));
                result_g1(1) := (g1(1) and bits(0));
                result_g1(2) := (g1(2) and bits(1));
                msg4 := result_g1(0) xor result_g1(1) xor result_g1(2);  --mod2
    
            when K2 =>
                result_g0(0) := (g0(0) and bits(0));
                result_g0(1) := (g0(1) and bits(1));
                result_g0(2) := (g0(2) and bits(2));
                msg5 := result_g0(0) xor result_g0(1) xor result_g0(2);  --mod2
                
                result_g1(0) := (g1(0) and bits(0));
                result_g1(1) := (g1(1) and bits(1));
                result_g1(2) := (g1(2) and bits(2));
                msg6 := result_g1(0) xor result_g1(1) xor result_g1(2);  --mod2
                
            when K3 =>
            when K4 =>
            [....................]
            MSG <= msg1 & msg2 & msg3 & msg4 & msg5 & msg6 & [.........];
        end case; 
    end if;
end process;

final_bit <= MSG;
end Behavioral;
end Behavioral;

I need something like this, but working : msg <= ((g0(0) * p0(0)) + (g0(1) * p0(1)) + (g0(2) * bits(0)) mod 2); Main problem is that signal bits have to be vector

I need to perform bitwise operations to get a 0 or 1 result from msg1 and msg2. Then, I want to concatenate these results into MSG, resulting in a 32-bit output from 16 bits of input information. Do you think there is a smarter way?

I will be really glad for your help!

Like this

process(g0, p0, bits)
    variable result: std_logic_vector(2 downto 0);  -- Temporary result
    variable sum: std_logic := '0';  -- Sum (mod 2) initialization
begin
    -- Perform element-wise multiplication and accumulate the result
    result(0) := (g0(0) and p0(0));
    result(1) := (g0(1) and p0(1));
    result(2) := (g0(2) and bits(0));

    -- Sum all the results and take mod 2 (XOR is equivalent to addition mod 2)
    sum := result(0) xor result(1) xor result(2);

    -- Assign the result to the output
    msg <= sum;
end process;