How to generate Verilog rather than SystemVerilog from Chisel?

Here is my GCD.scala

package gcd

import chisel3._

class GCD extends Module {
  val io = IO(new Bundle {
    val value1        = Input(UInt(16.W))
    val value2        = Input(UInt(16.W))
    val loadingValues = Input(Bool())
    val outputGCD     = Output(UInt(16.W))
    val outputValid   = Output(Bool())
  })

  val x = Reg(UInt())
  val y = Reg(UInt())

  when(x > y) { x := x - y }.otherwise { y := y - x }

  when(io.loadingValues) {
    x := io.value1
    y := io.value2
  }

  io.outputGCD   := x
  io.outputValid := y === 0.U
}

object Elaborate extends App {
  val firtoolOptions = Array("--lowering-options=" + List(
    "disallowLocalVariables",
    "disallowPackedArrays",
    "locationInfoStyle=wrapInAtSquareBracket"
  ).reduce(_ + "," + _))
  circt.stage.ChiselStage.emitSystemVerilogFile(new gcd.GCD(), args, firtoolOptions)
}

I'm using Chisel 6.4.0:

ivy"org.chipsalliance::chisel:6.4.0"
ivy"org.chipsalliance:::chisel-plugin:6.4.0"
ivy"edu.berkeley.cs::chiseltest:6.0.0"

It seems Chisel 6 will emit systemverilog by default.

When I switch to Chisel 3, getVerilogString() is useful to generate verilog, but it will also generate systemverilog from Chisel 6.4.0.

I've searched for lots of solutions, they all solved based on Chisel 3.

How can I generate verilog from Chisel 6.4.0 ?

There is not a way in Chisel 6 to emit Verilog specifically. To our (the developers') knowledge, all tools support some SystemVerilog so Verilog itself is not a priority.

If there is an issue with a particular tool, then please see all of the available options in firtool's --lowering-options argument which allows you to remove certain SystemVerilog features. You are already providing the two most common ones that some tools struggle with disallowLocalVariables and disallowPackedArrays, but if you still have issues, try some of the other options. You can see everything that's available by passing --help to firtool.