I have to run an rtl simulation where all the source codes are verilog (system verilog) files but a module of my interest is a gate netlist module. Of course I have to put some wire delays around the instantiated gate netlist module to avoid timing errors. The problem is, the netlist module's input and output ports have been all split into separate bits by the placement and route tool(it went through some ECO operation). So originally the module definition started like :
module abc (
input [15:0] a;
output [7:0] b;
..
but now it has become
module abc (
input \a[15] ;
input \a[14] ;
input \a[13] ;
input \a[12] ;
input \a[11] ;
...
output \b[7] ;
output \b[6] ;
output \b[5] ;
output \b[4] ;
...
Now, in the module "eee" which instantiates the module "abc", I used to have it like
wire [15:0] sig_a;
wire [7:0] sig_b;
abc u_abc (
.a(sig_a),
.b(sig_b),
...
But I cannot do the same because the compiler complains about it.
Port name 'a' of instance 'tb_aaa.bbb.ccc.ddd.eee' is invalid or has multiple connections and the instantiated module is defined in file abc_gate.v
I tried using generate for the port mapping of each bit but it looks like verilog doesn't allow generate statements for each group of port mapping. I don't want to modify the netlist. How can I solve this?
Some synthesis tools can be configured to preserve module port names such that the synthesized Verilog code matches the RTL code (for the port list). Refer to the Cadence documentation or contact Cadence.
If that is not a possibility, it is standard practice to handle pre-/post-synthesis differences by using Verilog macros. For example, in your Verilog code, you can define a macro such as GATES to conditionally instantiate the abc module:
`ifdef GATES
abc abc ( /* netlist port names here */ );
`else
abc abc ( /* RTL port names here */ );
`endif