What are the number of accesses of the code:
MOV R1, R0
STR R4,[R1,#4]!
LDR R3,[R1]
R1-R4 are all 32 bits.
The answer is five and I'm genuinely confused. Can anyone help me with that? So far I understand MOV does not require memory access, and my guess is two for STR and one for LDR. STR access the memory of R1 and R1+4; while LDR access the memory of R1. But I don't think this is the right explanation, and I don't know which operations account to the addtional 2 memory accesses. Any help would be appreciated!
Answered by Peter Cordes
They're probably counting instruction-fetch: 3 instructions plus a load and a store. Registers aren't memory. Some microarchitectures fetch blocks of machine code in wider chunks (and even decode multiple instructions per cycle in parallel), but those uarches would have an I-cache (or a unified L1 cache on older ARMs). So there'd be 2 data cache accesses (load + store) and one or two I-cache accesses on a high-performance CPU.