Error (10170): HDL syntax errors in Quartus (HDL)

Can anyone see what is wrong with my code?

I copied the code from the article, but the code in it works without errors.

These are the errors:

module sqrt #(
    parameter WIDTH=8,  // width of radicand
    parameter FBITS=0   // fractional bits (for fixed point)
    ) (
    input wire logic clk,
    input wire logic start,             // start signal
    output     logic busy,              // calculation in progress
    output     logic valid,             // root and rem are valid
    input wire logic [WIDTH-1:0] rad,   // radicand
    output     logic [WIDTH-1:0] root,  // root
    output     logic [WIDTH-1:0] rem    // remainder
    );

    logic [WIDTH-1:0] x, x_next;    // radicand copy
    logic [WIDTH-1:0] q, q_next;    // intermediate root (quotient)
    logic [WIDTH+1:0] ac, ac_next;  // accumulator (2 bits wider)
    logic [WIDTH+1:0] test_res;     // sign test result (2 bits wider)

    localparam ITER = (WIDTH+FBITS) >> 1;  // iterations are half radicand+fbits width
    logic [$clog2(ITER)-1:0] i;            // iteration counter

    always_comb begin
        test_res = ac - {q, 2'b01};
        if (test_res[WIDTH+1] == 0) begin  // test_res ≥0? (check MSB)
            {ac_next, x_next} = {test_res[WIDTH-1:0], x, 2'b0};
            q_next = {q[WIDTH-2:0], 1'b1};
        end else begin
            {ac_next, x_next} = {ac[WIDTH-1:0], x, 2'b0};
            q_next = q << 1;
        end
    end

    always_ff @(posedge clk) begin
        if (start) begin
            busy <= 1;
            valid <= 0;
            i <= 0;
            q <= 0;
            {ac, x} <= {{WIDTH{1'b0}}, rad, 2'b0};
        end else if (busy) begin
            if (i == ITER-1) begin  // we're done
                busy <= 0;
                valid <= 1;
                root <= q_next;
                rem <= ac_next[WIDTH+1:2];  // undo final shift
            end else begin  // next iteration
                i <= i + 1;
                x <= x_next;
                ac <= ac_next;
                q <= q_next;
            end
        end
    end
endmodule

and the error messages appear in the last paragraph:

1. Error (10170): Verilog HDL syntax error at sqrtvg.sv(5) near text "logic"; expecting an identifier ("logic" is a reserved keyword ), or "[", or "signed", or "unsigned"
2. Error (10170): Verilog HDL syntax error at sqrtvg.sv(6) near text "logic"; expecting an identifier ("logic" is a reserved keyword ), or "[", or "signed", or "unsigned"
3. Error (10170): Verilog HDL syntax error at sqrtvg.sv(9) near text "logic"; expecting an identifier ("logic" is a reserved keyword ), or "[", or "signed", or "unsigned"
4. Error (10112): Ignored design unit "sqrtvg" at sqrtvg.sv(1) due to previous errors

I tried to remove the word "wire" from the input.

The code compiles without errors on many other simulators. Try it with other simulators on EDA Playground.

You need to read the Quartus documentation to understand why it does not support these SystemVerilog features. Perhaps it is a bug in the tool, and you need to update to a newer version of Quartus.

You do not need to declare the module ports using the logic keyword. Also, reg is a synonym for logic. Perhaps this will allow your code to compile (logic removed from input ports, and logic changed to reg for output ports):

input wire  clk,
input wire  start,                 // start signal
output      reg busy,              // calculation in progress
output      reg valid,             // root and rem are valid
input wire  [WIDTH-1:0] rad,       // radicand
output      reg [WIDTH-1:0] root,  // root
output      reg [WIDTH-1:0] rem    // remainder

Refer to IEEE Std 1800-2023 section 23.2.2.3 Rules for determining port kind, data type, and direction:

If the data type is omitted, it shall default to logic