I've generated dependency files (*.d) automatically with make (using g++ -MMD), and in these files I see that the rules created don't have any recipes. Moreover, from my testing, I've noticed that subsequent builds (after *.d have been created) will still use the recipe that I defined myself in the Makefile:
CPPFLAGS := -Iinclude
CXXFLAGS := -std=c++20 -Wall -Wextra -Werror -MMD
%.o: %.cpp
# recipe below used when building from dependency files!
$(CXX) -c $(CPPFLAGS) $(CXXFLAGS) -o$@ $<
-include $(DEPS_FILES)
Is it mentioned somewhere in the documentation that a rule with an empty recipe just adds prerequisites to existing rules? I'm asking because I noticed that it doesn't use the implicit rules defined here.
in these files I see that the rules created don't have any recipes.
Yes, that's normal. There can be at most one recipe for any given target, and GCC cannot presume to know what that's supposed to be.
The GNU manual discusses rules without recipes in multiple places, but it can perhaps be faulted for not explicitly saying in the "Rule Syntax" section that rules without recipes are allowed.
Is it mentioned somewhere in the documentation that a rule with an empty recipe just adds prerequisites to existing rules?
Yes, at the top of section 4.11, "Multiple Rules for One Target":
One file can be the target of several rules. All the prerequisites mentioned in all the rules are merged into one list of prerequisites for the target. If the target is older than any prerequisite from any rule, the recipe is executed.
This is a longtime feature of Unix make, not a GNU innovation.
I'm asking because I noticed that it doesn't use the implicit rules
Not where you provide explicit rules for the targets that need to be built, no. Implicit rules are considered only in the event that no explicit rule for a given target provides a recipe.