Intel manual states that one need to check CPUID.01:EDX[5] to see if RDMSR and WRMSR instructions are available. If, using CPUID, I already found that a particular bit of a particular MSR (in my case IA32_EFER.NXE) is supported, does it automatically means that RDMSR and WRMSR are supported too. Logically, this should be the case but I didn't see it explicitely stated.
I think it's a safe assumption that MSR-existence feature bits imply rdmsr and wrmsr and thus the CPUID feature bit for those instructions.
I could only imagine an emulated Deathstation 9000 x86 CPUs having intentional pitfalls like that intentionally, and it wouldn't happen by accident. Real CPUs that support NX are also new enough to have MSRs. On real CPUs, you can even make assumptions like SSE4.1 implying SSSE3, since Intel numbered SIMD extensions have already been incremental. (I say "numbered" to exclude things like AVX-512 VP2INTERSECT which doesn't build on any others and is actually gone from some CPUs that have some later AVX-512 features.)
CPUs that don't have any MSRs wouldn't have a CPUID feature bit set for a feature that would effectively do nothing without MSRs.