Getting "Bus start index should be less than or equal to bus end index" even though it is less

I am trying to create the ALU chip, however I am running into this error:

Bus start index should be less than or equal to bus end index

whenever I try to split the output using indecies.

This is my code for the ALU chip:

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/2/ALU.hdl
/**
 * ALU (Arithmetic Logic Unit):
 * Computes out = one of the following functions:
 *                0, 1, -1,
 *                x, y, !x, !y, -x, -y,
 *                x + 1, y + 1, x - 1, y - 1,
 *                x + y, x - y, y - x,
 *                x & y, x | y
 * on the 16-bit inputs x, y,
 * according to the input bits zx, nx, zy, ny, f, no.
 * In addition, computes the two output bits:
 * if (out == 0) zr = 1, else zr = 0
 * if (out < 0)  ng = 1, else ng = 0
 */
// Implementation: Manipulates the x and y inputs
// and operates on the resulting values, as follows:
// if (zx == 1) sets x = 0        // 16-bit constant
// if (nx == 1) sets x = !x       // bitwise not
// if (zy == 1) sets y = 0        // 16-bit constant
// if (ny == 1) sets y = !y       // bitwise not
// if (f == 1)  sets out = x + y  // integer 2's complement addition
// if (f == 0)  sets out = x & y  // bitwise and
// if (no == 1) sets out = !out   // bitwise not

CHIP ALU {
    IN  
        x[16], y[16],  // 16-bit inputs        
        zx, // zero the x input?
        nx, // negate the x input?
        zy, // zero the y input?
        ny, // negate the y input?
        f,  // compute (out = x + y) or (out = x & y)?
        no; // negate the out output?
    OUT 
        out[16], // 16-bit output
        zr,      // if (out == 0) equals 1, else 0
        ng;      // if (out < 0)  equals 1, else 0

    PARTS:
        // ZERO THE OUTPUT? => x1, y1
        Mux16(a=x , b=false , sel=zx , out=x1 );
        Mux16(a=y , b=false , sel=zy , out=y1 );

        // NEGATE THE OUTPUT? => x2, y2

        Not16(in=x1 , out=nx1 );
        Not16(in=y1 , out=ny1 );

        // IF nx, ny: nx1, ny1 ELSE x1, y1 => x2, y2
        Mux16(a=x1 , b=nx1 , sel=nx , out=x2 );
        Mux16(a=y1 , b=ny1 , sel=ny , out=y2 );

        // SUM, AND => fsum, fand
        Add16(a=x2 , b=y2 , out=fsum );
        And16(a=x2 , b=y2 , out=fand );

        // IF f => fsum ELSE fand
        Mux16(a=fand , b=fsum , sel=f , out=fOut );
        
        // NEGATE OUTPUT? => o1
        Not16(in=fOut , out=nfOut );

        // IF no => nfOut ELSE fOut
        Mux16(a=fOut , b=nfOut , sel=no , out=out, out[15]=ng, out[0...7]=h1, out[8...15]=h2);

        // check if there are 1s in the output
        Or8Way(in=h1 , out=orh1 );
        Or8Way(in=h2 , out=orh2 );
        Or(a=orh1 , b=orh2 , out=zr );


}

This is the problematic line:

Mux16(a=fOut , b=nfOut , sel=no , out=out, out[15]=ng, out[0...7]=h1, out[8...15]=h2);

The IDE highlits out[8...15]=h2, and the start index is obviously less or equal than the end index, so what could possibly be the issue here?

I tried seperating all the outputs into multiple lines, however the issue persists. Like so:

Mux16(a=fOut , b=nfOut , sel=no , out[8...15]=h2);
Mux16(a=fOut , b=nfOut , sel=no , out[0...7]=h1);
Mux16(a=fOut , b=nfOut , sel=no , out[15]=ng);
Mux16(a=fOut , b=nfOut , sel=no , out=out);

And I get the same error on this line Mux16(a=fOut , b=nfOut , sel=no , out[8...15]=h2);

I ended up just manually ORing each bit, but I wonder why this gives an error?

If memory serves, the format for definding a sub-bus is [from..to], not [from...to].