verilogsystem-verilogiverilog

verilog LRM 23.3.3.1 connecting output to output

From the LRM:

23.3.3.1 Port coercion A port that is declared as input (output) but used as an output (input) or inout may be coerced to inout. If not coerced to inout, a warning shall be issued.

The LRM doesn't make sense, shouldn't it be the opposite if coerced i.e simulator is changing rtl "under the hood" warning shall be issued. If not coerced to inout compilation should fail (as lint and synthesis) ?

test case : https://www.edaplayground.com/x/VdmF

related : What is the exact criteria for an inout port, when sometimes inout and output ports can be interchangeably used in Verilog?

Solution

  • The Verilog standard is incorrect and has been since IEEE 1364-1995. The problem is most simulation tools ignore port directions and no one has put in the effort to fix the LRM.

    https://accellera.mantishub.io/view.php?id=1289