I'm currently working on a simple project on an FPGA and wanted to set an enable-input to 1. Now when using the built in IPs for a constant, two components show up. One is "Constant" and the other is "Inline constant". I see no difference when used.
I can't seem to find any documentation showing the difference and all customizability and visuals for the two components seem to be identical apart from the name.
What is the difference and why should I use one over the other?
(I've attached images to show the two types of constants I'm talking about: The options in Vivado & expanded Vivado view)
Inline Utility IPs were added in Vivado 2024.2 (I can't see reference to them in 2024.1).
Vivado claims that using these reduces disk usage. I haven't used these yet, but it suggests that they don't get an Out of Context run anymore, and are instead folded into the top level Verilog / VHDL source file that is generated:
https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/Inline-HDL
2024.2 and newer will automatically prompt to migrate to these when you open an older project:
https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/Migrating-Utility-IPs-to-Inline-HDL
Edit: Just tried to use "Inline Constant" in a design to drive a width 1 signal. Unfortunately, the way it is implemented in VHDL is it assigns using X"0". This has a width of 4, not 1. So the synthesiser errors out.
This can be avoided by setting "Inline Constant" to a width of a multiple of 4, and using that instead. I ended up using an "Inline Utility Reduced Logic" to get down to 1 bit.
