I was reading the lecture notes here about Demand Paging. The author states that:
- Restarting process execution after a page fault is tricky, since the fault may have occurred in the middle of an instruction.
- If instructions are idempotent, just restart the faulting instruction (hardware saves instruction address during page fault).
How does idempotence, specifically instruction idempotence, make restarting the instruction easy? How is idempotence related in restarting instructions?
This appears to be mental masturbation intended to make the simple complex. The mathematician in me cringes at the usage of "idempotence" here. Yes, there are "idempotent" instructions
MOV #1, R0
But in nearly all cases instructions are not idempotent. So why confuse students with such needless terminology.
Things a much simpler than suggested there
A processor will only allow faults in places where it can restart. On processors with instructions that can take a "long time" (such a string/memory move), they usually keep track of progresss using registers. If a page fault occurs in such an instruction, restarting picks up whether the processor left off. The processsor does not go back and restart the entire instruction.
The MOVC5/MOVC3 instructions here do that.
https://vmssoftware.com/docs/VAX_MACRO_INSTRUCTION_SET_REF.pdf
So does REP MOVS
https://opensecuritytraining.info/IntroX86-64_files/IntroductionToIntelx86-64-12_RepMovs-Done.pdf
If the processor allows interrupts in the middle of an instruction withut using registers for context, it has to save additional information so that the instruction can be restarted midway through..
If restarting instruction were difficult for a page fault handler, operating systems would have been screwed over decades ago.
I also note that I have never seen a +(SP) addressing mode before. I have seen -(SP) and (SP)+ but not +(SP).