I'm trying to test a module which takes as input a UInt that follows the structure of this Bundle:
class Sample(n_attr: Int, n_classes: Int, n_depths: Int, info_bit: Int, tree_bit: Int) extends Bundle{
val features = Vec(n_attr, FixedPoint(32.W,16.BP))
val offset = UInt(info_bit.W)
val shift = Bool()
val search_for_root = Bool()
val tree_to_exec = UInt(tree_bit.W)
val scores = Vec(n_classes,FixedPoint(16.W,8.BP))
val weights = Vec(n_depths, FixedPoint(16.W,8.BP))
val dest = Bool()
val last = Bool()
val clock_cycles = UInt(32.W)
}
To avoid creating a binary string by hand (it would be 256 bits long) I'm trying to use Bundl literals like so:
c.wrapper_io.sample_in.TDATA.poke((new Sample(n_attr, n_classes, n_depths, info_bit, tree_bit)).Lit(
_.features -> VecInit(0.F(8.BP), 0.F(8.BP), 0.F(8.BP), 0.F(8.BP), 0.F(8.BP)),
_.offset -> 0.F(8.BP),
_.shift -> false.B,
_.search_for_root -> false.B,
_.tree_to_exec -> 0.F(8.BP),
_.scores -> VecInit(0.F(8.BP), 0.F(8.BP), 0.F(8.BP), 0.F(8.BP), 0.F(8.BP), 0.F(8.BP)),
_.weights -> VecInit(0.F(8.BP), 0.F(8.BP), 0.F(8.BP), 0.F(8.BP), 0.F(8.BP), 0.F(8.BP)),
_.dest -> false.B,
_.last -> false.B,
_.clock_cycles -> 0.U,
).litValue.U)
But when I try to compile I get the following error:
Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox.
Is there a way to initialize Vecs inside Bundle literals? Thanks for the help!
I don't know how I missed it, but I found there is a way to do spcecifically this in the documentation. Here is how I fixed my code (there are a few other differences):
c.wrapper_io.sample_in.TDATA.poke((new Sample(n_attr, n_classes, n_depths, info_bit, tree_bit)).Lit(
_.features -> Vec.Lit(0.0.F(32.W, 16.BP), 0.0.F(32.W, 16.BP), 0.0.F(32.W, 16.BP), 0.0.F(32.W, 16.BP), 0.0.F(32.W, 16.BP)),
_.offset -> 0.U,
_.shift -> false.B,
_.search_for_root -> false.B,
_.tree_to_exec -> 0.U,
_.scores -> Vec.Lit(0.0.F(16.W, 8.BP), 0.0.F(16.W, 8.BP), 0.0.F(16.W, 8.BP), 0.0.F(16.W, 8.BP), 0.0.F(16.W, 8.BP), 0.0.F(16.W, 8.BP)),
_.weights -> Vec.Lit(0.0.F(16.W, 8.BP)),
_.dest -> false.B,
_.last -> false.B,
_.clock_cycles -> 0.U,
).litValue.U(best_width.W))
I also imported this:
import chisel3.experimental.VecLiterals._