STM32H7.cpu0 not halted using OpenOCD

I have come across an issue recently where I encounter issues when trying to flash my STM32H723VET6 (single-core Cortex-M7) MCU on a custom PCB using OpenOCD in a linux (ubuntu) terminal environment. I am using a cheap ST-Link V2 clone to flash code as shown in the picture. I am using Serial Wire (VCC, GND, SWDIO, SWCLK,) and therefore only have these connected.

The connections can be seen in the PCB Setup picture, where the red cable is power, the grey cable is ground, the blue cable is SWDIO, and the white cable is SWCLK. The header pin next to these connections is the NRST terminal, which if the leads are shorted together, the MCU enters reset mode.

The OpenOCD commands I use are:

openocd -d2 -f /usr/share/openocd/scripts/interface/stlink-v2.cfg -f /usr/share/openocd/scripts/target/stm32h7x.cfg -c "init" -c "reset halt" -c "flash write_image erase build/USLI_H723.bin 0x08000000" -c "reset" -c "shutdown"

and

openocd -d2 -f /usr/share/openocd/scripts/interface/stlink-v2.cfg -f /usr/share/openocd/scripts/target/stm32h7x.cfg -c "program build/USLI_H723.elf verify reset exit"

However, everytime I try to do so, I get the following log:

    Open On-Chip Debugger 0.11.0
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
debug_level: 2

WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg
Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'.
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Info : clock speed 1800 kHz
Info : STLINK V2J45S7 (API v2) VID:PID 0483:3748
Info : Target voltage: 3.215243
Info : stm32h7x.cpu0: hardware has 8 breakpoints, 4 watchpoints
Info : starting gdb server for stm32h7x.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
Error: timed out while waiting for target halted
TARGET: stm32h7x.cpu0 - Not halted

and

Open On-Chip Debugger 0.11.0
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
debug_level: 2

WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg
Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'.
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Info : clock speed 1800 kHz
Info : STLINK V2J45S7 (API v2) VID:PID 0483:3748
Info : Target voltage: 3.217895
Info : stm32h7x.cpu0: hardware has 8 breakpoints, 4 watchpoints
Info : starting gdb server for stm32h7x.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
Error: timed out while waiting for target halted
** Unable to reset target **
shutdown command invoked

make: *** [Makefile:227: load] Error 1

, respectively.

Upon reading into some issues concerning the MCU not having a proper software reset, I used the following command:

openocd -d2 -f /usr/share/openocd/scripts/interface/stlink-v2.cfg -f /usr/share/openocd/scripts/target/stm32h7x.cfg -c "reset_config srst_only srst_nogate connect_assert_srst" -c "init" -c "reset halt" -c "flash write_image erase build/USLI_H723.bin 0x08000000" -c "reset" -c "shutdown"

However, that yieled the same result. I also tried connecting the ST-Link's RST to the NRST of the MCU, however, that didn't work either. Lastly, I tried playing around with BOOT0: (to be honest I didn't know what I was doing there, but) someone told me to short BOOT0 to VCC, power-on the chip, flash the code, power cycle it, and reset it, unfortunately, that didn't work either. Yet, when using GDB, everything flashes fine, or when using CubeProgrammer, no issues occur. But whenever I am using OpenOCD in this setup it doesn't seem to work, the only method working as of now is when I use a very short time frame when initializing the flash command, where I manually force the chip to reset by shorting the header leads together, but even that doesn't work all the time.

When manually force resetting the MCU, I receive this log:

Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
debug_level: 2

WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg
Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'.
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
srst_only separate srst_nogate srst_open_drain connect_assert_srst

Info : clock speed 1800 kHz
Info : STLINK V2J45S7 (API v2) VID:PID 0483:3748
Info : Target voltage: 3.218433
Info : stm32h7x.cpu0: hardware has 8 breakpoints, 4 watchpoints
Info : starting gdb server for stm32h7x.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
target halted due to debug-request, current mode: Thread 
xPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc
Info : Device: STM32H72x/73x
Info : flash size probed value 512
Info : STM32H7 flash has a single bank
Info : Bank (0) size is 512 kb, base address is 0x08000000
Info : Padding image section 0 at 0x0800fef8 with 8 bytes (bank write end alignment)
Warn : Adding extra erase range, 0x0800ff00 .. 0x0801ffff
auto erase enabled
wrote 65280 bytes from file build/USLI_H723.bin in 3.152524s (20.222 KiB/s)

target halted due to breakpoint, current mode: Thread 
xPSR: 0x61000000 pc: 0x20000064 msp: 0xfffffffc
shutdown command invoked

Any help will be appreciated, Thank you!

I appreciate all the details, but I think you have it solved in the first paragraph.

I am using Serial Wire (VCC, GND, SWDIO, SWCLK,) and therefore only have these connected.

The SWD protocol does expect the RESET line to be connected: https://developer.arm.com/documentation/101636/0100/Debug-and-Trace/JTAG-SWD-Interface, so program is failing because OpenOCD is trying to assert a reset line that isn't connected. Try connecting the RESET line on your "STLink" to the NRST signal on the chip.

This open OCD log line points you to that:

Error: timed out while waiting for target halted
** Unable to reset target **

----

For reference here's the point in the OpenOCD source where it configures STM32H7x targets to use the hardware reset line. "SRST" is what OpenOCD would call the NRST line on your chip.