Say I switch from user mode to system mode by executing ecall, which disables interrupts by setting SIE bit in sstatus to 0.
What will happen to an interrupt that occurs while interrupts are disabled?
There is a concept of pending interrupt, that reflects by the value of SIP register (or MIP on machine mode). That interrupt remains pending until the global interrupt enable (SIE) is restored, at which point, if the interrupt source is still active (or its pending bit remains set), the processor will take the interrupt trap.
If multiple interrupts occur while interrupts are disabled, their respective pending bits are all set. RISC‑V hardware generally assigns priorities to interrupts, so when you re‑enable interrupts, the highest‑priority pending interrupt is taken first.
So, in short, the interrupts are queued and should be handled in priority-order, after your ecall handler exits (with sret or mret).
The actual delivery behavior may depend on the exact interrupt source (e.g., level‐sensitive versus edge‐triggered), but generally, interrupts are latched as pending rather than ignored.
There is also an option of having nested interrupts, means handling interrupts while the handler still executes, but that's rather different and more complicated story.