[SOLVED] ERROR main.py:71: hdlmake() 'utf-8' codec can't decode

I am interested in building a project from a repository on GitHub: MEN A25 SBC PCIe-VME Bridge Gateware. I followed the steps provided for generating the FPGA bitstream:

Fetch all git submodules with git submodule update --init
Make sure you have HDLmake version greater than 3.3 (it should include at least commit 3ac2e4e, if unsure go for latest commit on the master branch).
Make sure you have Altera Quartus 16.0 installed, along with support for the Cyclone IV GX FPGA family.
Enter the hdl/syn folder and run hdlmake(make sure that Altera Quartus binaries are in your system path beforehand).
At this point you can either simply run make to build the project and generate the FPGA bitstream, or make project to only generate the Altera Quartus project files (A25_top.qsf and A25_top.qpf) which you can then open in the Quartus GUI and continue the build process in there.
Either way, if the process is successful, new files with name 16A025-00_MM_mm will be generated in hdl/syn/fpga_files. You should only use those files for programming the FPGA. Please note that the hdl/syn/A25_top.bin is not the right file, it will lead to a programmed FPGA with a missing bitstream header.

Here are the commands I ran:


[gms@localhost ~]$ su
Password: 
[root@localhost gms]# cd VME_test
[root@localhost VME_test]# git clone https://ohwr.org/project/vme-sbc-a25-pcie-vme-bridge.git
Cloning into 'vme-sbc-a25-pcie-vme-bridge'...
remote: Enumerating objects: 821, done.
remote: Counting objects: 100% (216/216), done.
remote: Compressing objects: 100% (168/168), done.
remote: Total 821 (delta 101), reused 48 (delta 48), pack-reused 605
Receiving objects: 100% (821/821), 7.90 MiB | 1.59 MiB/s, done.
Resolving deltas: 100% (381/381), done.
[root@localhost VME_test]# cd hdl/syn
[root@localhost syn]# git submodule init
Submodule 'general-cores' (https://ohwr.org/project/general-cores.git) registered for path '../../dependencies/general-cores'
Submodule 'vme-bridge' (https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/vme-bridge.git) registered for path '../../dependencies/vme-bridge'
[root@localhost syn]# git submodule update
Cloning into '/home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/dependencies/general-cores'...
Cloning into '/home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/dependencies/vme-bridge'...
Submodule path '../../dependencies/general-cores': checked out '3c636a53f7c6605fbb8c66093a3dcb08132a572c'
Submodule path '../../dependencies/vme-bridge': checked out 'e529102a1c05540a68588ebd74f8dd8e9ff4722a'
[root@localhost syn]# hdlmake fetch
INFO    <string>:14: <module>() Library component wb_fine_pulse_gen targets only xilinx devices
INFO    <string>:11: <module>() Library component wb_xc7_fw_update targets only xilinx devices
INFO    commands.py:120: fetch()    Fetching needed modules.
INFO    commands.py:130: fetch()    All modules fetched.
[root@localhost syn]# hdlmake
INFO    <string>:14: <module>() Library component wb_fine_pulse_gen targets only xilinx devices
INFO    <string>:11: <module>() Library component wb_xc7_fw_update targets only xilinx devices
INFO    action.py:139: build_file_set() Detected 2 supported files that are not parseable
INFO    action.py:141: build_file_set() not parseable: /home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/hdl/syn/A25_top.sdc
INFO    action.py:141: build_file_set() not parseable: /home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/hdl/16z091-01_src/Synthesis/z91_01_tmg_con.sdc
INFO    action.py:144: build_file_set() Detected 252 supported files that can be parsed
ERROR   main.py:71: hdlmake()   'utf-8' codec can't decode byte 0xfc in position 2405: invalid start byte
[root@localhost syn]# export PATH=$PATH:/home/intelFPGA/17.0/quartus/bin/
[root@localhost syn]# hdlmake
INFO    <string>:14: <module>() Library component wb_fine_pulse_gen targets only xilinx devices
INFO    <string>:11: <module>() Library component wb_xc7_fw_update targets only xilinx devices
INFO    action.py:139: build_file_set() Detected 2 supported files that are not parseable
INFO    action.py:141: build_file_set() not parseable: /home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/hdl/16z091-01_src/Synthesis/z91_01_tmg_con.sdc
INFO    action.py:141: build_file_set() not parseable: /home/gms/VME_test/vme-sbc-a25-pcie-vme-bridge/hdl/syn/A25_top.sdc
INFO    action.py:144: build_file_set() Detected 252 supported files that can be parsed
ERROR   main.py:71: hdlmake()   'utf-8' codec can't decode byte 0x96 in position 1906: invalid start byte

I am stopped at this error bash ERROR main.py:71: hdlmake() 'utf-8' codec can't decode I have Quartus 17.0 installed, but I am not sure if my HDLmake version is greater than 3.3 (#2) because when I installed HDLmake, I saw this prompt:

[root@localhost hdl-make]# python3.6 setup.py install
hdlmake 3.3 is already the active version in easy-install.pth
Installing hdlmake script to /usr/local/bin

Installed /usr/local/lib/python3.6/site-packages/hdlmake-3.3-py3.6.egg
Processing dependencies for hdlmake==3.3
Finished processing dependencies for hdlmake==3.3

Please advise. Thank you.