Refer to this question,I write a similar case.
module n;
reg [1:0]a, b;
initial begin
a=1;
a<=a+1;
$strobe("strobe",a);
$display("display",a);
end
endmodule
The output is:
display 1
strobe 2
Refer to @toolic answer of refered question,
Then, still at time=0, you increment a by 1 with a<=a+1. This means a becomes 2 at time=0.
I have 2 questions:
1.As a become 2 at time 0,why $strobe and $display output different result for the same target?
2.In the begin end block,why $display output advance than $strobe?
verilog simulation time stamp consists of multiple phases. For understanding of your problem it is sufficient to notice that there are 'blocking' assignment phase and non-blocking assignment phase. It means that verilog will go through all statements in your 'initial' or an always block, and execute all '=' assignments and schedule all of the '<=' assignments to be done next, in the non-blocking phase.
While doing so, it will also execute all $display statements immediately during this blocking assignment phase. But it will schedule execution of $strobe at the very end of the time stamp, after all blocking and non-blocking assignments are done. This exactly the purpose of $strobe.
Therefore the results you see are expected. $display shows results from the blocking phase and $strobe shows results after non-blocking phase.