system-verilogfpgaverificationuvmsynthesis

Should UVM testbench work with pre-synthesis or post-synthesis FPGA code?

I’m working on an FPGA project and planning to use UVM (Universal Verification Methodology) for verification. I’m confused about the timing of when to apply UVM in the design flow.

Should I develop my UVM testbench to work with:

  1. Pre-synthesis RTL code (Verilog/SystemVerilog behavioral code)
  2. Post-synthesis netlist (gate-level implementation)

I understand that UVM is a verification methodology, but I want to make sure I’m applying it at the correct stage of the FPGA design flow.

What is the standard practice in the industry? Any insights about the verification flow would be appreciated.

Solution

  • Ideally, you would use the same testbench code with both the RTL design and the gate-level design. In practice, it is challenging to run simulations using the exact same testbench code on both design views. However, you can usually get very close.

    The same approach applies no matter what verification flow you use (UVM or any other).