`timescale 1ns/1ps
module m_top
(
input GCLK,
input [7:0] i_in1,
output o_out1,
output reg o_out2,
inout io_data,
output reg[7:0]yy
);
assign o_out1=5;
initial o_out2=6;
task my_task;
input a,b;
output c;
assign c=a+b;
endtask
my_task(o_out1,o_out2,yy);
endmodule
I got error when running verilog script:
ERROR: [VRFC 10-2063] Module <my_task> not found while processing module instance <'Undefined'>
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
Where is the problem? Thanks in advance.
In Verilog, a task needs to be called from a procedural block (initial or always) or from another task.
More on task enabling reference: verilog-std-1364-2005
section 10.2 Tasks & Task Enabling. IEEE 1394
Here is your posted code with the task called two ways (from always, from initial) and some comments about when to use one or the other.
Both compile without error.
Call from always block:
Use to model combinational logic in synthesizable RTL code.
`timescale 1ns/1ps
module m_top
(
input GCLK,
input [7:0] i_in1,
output o_out1,
output reg o_out2,
inout io_data,
output reg[7:0]yy
);
task my_task;
input a,b;
output c;
assign c=a+b;
endtask
assign o_out1=5;
initial o_out2=6;
// called from always @*
// models combinational logic
always @* begin
my_task(o_out1,o_out2,yy);
end
endmodule
Call from initial block:
Executes one time at t=0.
Use in a testbench.
Initial block use is not strictly limited to testbench.
Some synthesis tools support one time t=0 stuff like signal initialization or reading in ROM content into a memory using initial blocks.
`timescale 1ns/1ps
module m_top
(
input GCLK,
input [7:0] i_in1,
output o_out1,
output reg o_out2,
inout io_data,
output reg[7:0]yy
);
task my_task;
input a,b;
output c;
assign c=a+b;
endtask
assign o_out1=5;
// called from initial block (testbench style)
initial begin
o_out2=6;
my_task(o_out1,o_out2,yy);
end
endmodule