verilog

Is `x==1'bx` in Verilog?


In Verilog, $display("%b",^ 3'b10x); outputs x.

As x==1'dx, I believe ^ 3'b10x==1'bx is true, but the result is false.

What's the correct result of ^ 3'b10x?

And why is ^ 3'b10x==1'bx false?


Solution

  • You have an operator precedence confusion. == binds tighter than ^, so your expression is interpreted as ^ (3'b10x==1'bx). Unexpected, perhaps, but those are the rules:

    https://documentation-rp-test.readthedocs.io/en/latest/tutorfpga04.html