verilogsystem-verilog

How to define a module with a parameter in Verilog?

I want to define an add module which has a parameter, but my declaration of the new instance doesn't go well.

I want to define an instance of this module:

module add #(parameter wd=1) (input wire [wd-1:0] a,b, output wire [wd-1:0] o);

   assign o = a + b;

endmodule

I tried this line, but I get an error:

 add len_plus_1 #(8)(.a(len),.b(8'h1),.o(lenPlus1));
Solution

  • The instance name must come after the parameter specifier:

    add #(8) len_plus_1 (.a(len),.b(8'h1),.o(lenPlus1));

    This syntax is specified in the IEEE Standard (1800-2009, for example).