VHDL compiler exiting error

I am creating a test bench for a BCD_counter.

When i try to compile the test bench, i consistently get the error that reads:

"Error: .../.../../Test_UpDownCounter.vhdl(38): VHDL Compiler exiting."

This is the only error I am getting, and line 38 is the last line of my code. I am wondering what could be the problem?

Here is my code, any help will be much appreciated.

entity test_BCD is
  end entity test_BCD;

  architecture test of test_BCD is 
     signal t_clk, t_direction, t_init, t_enable: bit;
     signal t_q : integer;

     component UpDownCounter is 
          port(clk, direction, init, enable: in bit;
              q_out: out integer);
     end component;

     begin
       my_design: UpDownCounter port map (t_enable, t_q, t_clk, t_direction, t_init, t_enable);


       clk_gen: process
          constant High_time : Time :=5 ns;
          constant Low_time : Time := 5 ns;
       begin
          wait for High_time;
          t_clk <= '1';
          wait for Low_time;
          t_clk <= '0';
       end process clk_gen; 


       -- Initialization process (code that executes only once).
       init: process
       begin 
          -- enable signal
          t_enable <= '1', '0' after 100 ns, '1' after 200 ns;
          t_direction <= '1', '0' after 50 ns, '1' after 100 ns, '0' after 150 ns;
          t_init <= '0', '1' after 20 ns, '0' after 30 nz, '1' after 150 ns;
          wait;
       end process init;
end architecture test;

Solution

This line:

t_init <= '0', '1' after 20 ns, '0' after 30 nz, '1' after 150 ns;

has nz rather than (I assume) ns as the time units. Which my compiler tells me straight away:

** Error: test1.vhd(34): (vcom-1136) Unknown identifier "nz".

I'd raise a bug report with whatever compiler that it to generate better error messages!

While I'm here:

Your instantiation of UpDownCounter looks wrong - your signals look to be in a different order to the component declaration you've used.

And in this:

 clk_gen: process
      constant High_time : Time :=5 ns;
      constant Low_time : Time := 5 ns;
   begin
      wait for High_time;
      t_clk <= '1';
      wait for Low_time;
      t_clk <= '0';
   end process clk_gen;

Your labels High_time and Low_time are back to front - try changing one of them and see whether the high or low ime changes as you expect.