I have some doubts regarding the usage of PLD instruction in ARM cortex A8. As I am using the instruction inside loop, there is a possibility of out of bound memory access. My doubt is that whether that would cause a segmentation fault or not. I read in the ARM manual which states that
Because a PLD instruction is handled as any other load instruction by all levels of cache, the PLD instruction follows standard data-dependency rules and eviction procedures. During any stage of PLD execution, the PLD instruction is ignored in case of an address translation fault, a cache hit, or an abort.
So, if an out of bound memory access is made, the corresponding PLD instruction is ignored or not is my doubt.
PLD instruction doesn't create segmentation fault. In case PLD asks memory system to reach for a non existing memory area, it is ignored.
From ARM ARM
The Preload instructions are hints, and so implementations can treat them as NOPs without affecting the functional behavior of the device. The instructions do not generate synchronous Data Abort exceptions, but the memory system operations might, under exceptional circumstances, generate asynchronous aborts.
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However, a memory operation performed as a result of one of these memory system hints might trigger an asynchronous event, so influencing the execution of the processor. Examples of the asynchronous events that might be triggered are asynchronous aborts and interrupts.