Behavioral verilog bcd up down counter with enable and reset

I recently need to make a BCD up down counter with enable and reset. I have three always blocks but i dont know how to connect them together.

I have my code from code segments given by my teacher. I wrote a structural verilog doing the same function before and I have no idea how to convert it to a behavioral type.

Here is my code:

module BCDcountmod(Clock, Clear, E, segment_a, segment_b, segment_c, 
segment_d,  segment_e, segment_f, segment_g, updown);
input Clock, Clear, E, updown;
output segment_a, segment_b, segment_c, segment_d, segment_e, segment_f, segment_g;
reg    [6:0] segment_data;
reg    [3:0] BCD1, BCD0;

always @(posedge Clock)
begin
if (Clear)
    begin
        BCD1 <= 0;
        BCD0 <= 0;
    end

else if (E)
    if (updown)
        if (BCD0 == 4′b1001)
            begin
                BCD0 <= 0;
            if (BCD1 == 4′b0101)
                BCD1 <= 0;
            else
                BCD1 <= BCD1 + 1;
            end
        else
            BCD0 <= BCD0 + 1;
    end
    else
        if (BCD0 == 4'b0000)
            begin
                BCD0 <= 4'b1001;
            if (BCD1 == 4'b0000)
                BCD1 <= 4'b0101;
            else
                BCD1 <= BCD1 - 1;
            end
        else
            BCD0 <= BCD0 - 1;
    end
always @(BCD0)
case (BCD0)
    4'b0000: segment_data = 7'b1111110;
    4'b0001: segment_data = 7'b0110000;
    4'b0010: segment_data = 7'b1101101;
    4'b0011: segment_data = 7'b1111001;
    4'b0100: segment_data = 7'b0110011;
    4'b0101: segment_data = 7'b1011011;
    4'b0110: segment_data = 7'b1011111;
    4'b0111: segment_data = 7'b1110000;
    4'b1000: segment_data = 7'b1111111;
    4'b1001: segment_data = 7'b1111011;
endcase

wire segment_a = ~segment_data[6];
wire segment_b = ~segment_data[5];
wire segment_c = ~segment_data[4];
wire segment_d = ~segment_data[3];
wire segment_e = ~segment_data[2];
wire segment_f = ~segment_data[1];
wire segment_g = ~segment_data[0];

always @(BCD1)
case (BCD1)
    4'b0000: segment_data = 7'b1111110;
    4'b0001: segment_data = 7'b0110000;
    4'b0010: segment_data = 7'b1101101;
    4'b0011: segment_data = 7'b1111001;
    4'b0100: segment_data = 7'b0110011;
    4'b0101: segment_data = 7'b1011011;
endcase

wire segment_a = ~segment_data[6];
wire segment_b = ~segment_data[5];
wire segment_c = ~segment_data[4];
wire segment_d = ~segment_data[3];
wire segment_e = ~segment_data[2];
wire segment_f = ~segment_data[1];
wire segment_g = ~segment_data[0];

endmodule

With the current setup both digits are being driven to the same 7-segment display. To make matters worse, segment_data has competing drivers. For code reuse, create a new module for bcd to 7-segment conversion. For example:

module segment7dec (output reg [6:0] display, input [3:0] bcd);
  always @* begin
    case(bcd)
    4'b0000: display = 7'b1111110;
    4'b0001: display = 7'b0110000;
    4'b0010: display = 7'b1101101;
    4'b0011: display = 7'b1111001;
    4'b0100: display = 7'b0110011;
    4'b0101: display = 7'b1011011;
    4'b0110: display = 7'b1011111;
    4'b0111: display = 7'b1110000;
    4'b1000: display = 7'b1111111;
    4'b1001: display = 7'b1111011;
    default: display = 7'b0000000; //IMPORTANT, otherwise latches are inferred
    endcase
    display = ~display; // invert
  end
endmodule

Now connect the new module into BCDcountmod. Remember to remove the old segment_* code.

module BCDcountmod(
    input Clock, Clear, E, updown,
    output [6:0] display1, display0 );
  reg [3:0] BCD1, BCD0;
  always @(posedge Clock) begin
    /* Your logic for BCD1,BCD0
     *
     */
  end
  segment7dec disp1( .display(display1), .bcd(BCD1) );
  segment7dec disp0( .display(display0), .bcd(BCD0) );
endmodule

Example : http://www.edaplayground.com/s/6/398