Shift Register for std_logic_vector

I saw the same question here and i tried to follow the example but i ran into errors when declaring my signals. In specific:

#Error: COMP96_0015: Pipeline.vhd : (52, 44): ';' expected.

Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Pipeline isgeneric (
    VECTOR_WIDTH: natural := 128;
    VECTOR_DEPTH: natural := 7
); port(
     ImVal : in STD_LOGIC_VECTOR(9 downto 0);
     RA : in STD_LOGIC_VECTOR(127 downto 0);
     RB : in STD_LOGIC_VECTOR(127 downto 0);
     RC : in STD_LOGIC_VECTOR(127 downto 0);
     OpCode : in STD_LOGIC_VECTOR(10 downto 0);
     RT : in STD_LOGIC_VECTOR(127 downto 0);
     Clk: in STD_LOGIC;
     Reset: in STD_LOGIC;
     OutVal : out STD_LOGIC_VECTOR(127 downto 0)
 );
end Pipeline;

architecture Behavioral of Pipeline is
    type shift_reg_type1 is array (natural range<>) of std_logic_vector(127 downto 0);
    type shift_reg_type2 is array (natural range<>) of std_logic_vector(10 downto 0);
    type shift_reg_type3 is array (natural range<>) of std_logic_vector(9 downto 0);
    signal shift_regA: shift_reg_type1(0 to 6)(127 downto 0);
    signal shift_regB: shift_reg_type1(0 to 6)(127 downto 0);
    signal shift_regC: shift_reg_type1(0 to 6)(127 downto 0);
    signal shift_regT: shift_reg_type1(0 to 6)(127 downto 0);
    signal OpCode_reg: shift_reg_type2(0 to 6)(10 downto 0);
    signal ImVal_reg: shift_reg_type3(0 to 6)(9 downto 0);

begin

end Behavioral;

It is complaining about my signal declarations but i do not understand why.

Solution

The signal declarations are wrong as the error message say. Moreover it expects a semicolon because the statement is complete, but your code has two range constraints per signal...

signal shift_regA: shift_reg_type1(0 to 6);   
signal shift_regB: shift_reg_type1(0 to 6);  
signal shift_regC: shift_reg_type1(0 to 6);   
signal shift_regT: shift_reg_type1(0 to 6);   
signal OpCode_reg: shift_reg_type2(0 to 6);    
signal ImVal_reg: shift_reg_type3(0 to 6);

shift_reg_type1 is already constraint to 127..0. So can't constraint shift_regA again in the second dimension. Btw. there is no second dimension, because it's a 1 dimensional array of 1 dimensional elements.