RSA , no doubt, has several applications and is very famous. And today we use 2048-bit RSA key for security purposes. Yet, I see several research papers implementing RSA algorithm with 32-bit key (or more) on FPGAs.
Qasem Abu Al-Haija, Mahmoud Smadi, Monther Al-Ja'fari, Abdullah Al-Shua'ibi, Efficient FPGA Implementation of RSA Coprocessor Using Scalable Modules, Procedia Computer Science, Volume 34, 2014, Pages 647–654
Rohith S., Poornima, Mahesh C., FPGA Implementation of 16 bit RSA Cryptosystem for Text Message, International Journal of Computer Applications, Volume 92, No. 8, April 2014, 5 pp.
What is the purpose of it? 32-bit algorithm is easily crackable.
Why on FPGA?
Because a hardware implementation is more efficient and offloads the CPU. That is more relevant for small devices, think IoT.
Even if we do, then we end up with 32 or 64 bit key
That seems to be an artifact of the fact that this is research. One of those papers mentions "It is verified that this architecture support multiple key of 128bits, 256bits, and 512 bits"
Still not something I would like to use for my bank transactions but for data packets of low value, or only valuable or a short time period, even 128 bits might be acceptable.