I have c code runned from RAM in low power run mode (so interrupt are no handled). This mode enabled by code sequence:
So there no problem whith WFE instruction that described in errata sheet. Problem with this construction, it may be cause of CPU lock in low power wait mode forever:
while nbit(TIM1_SR1,CC3IF) asm("wfe");
that is disassembly as:
000035 720252B602 BTJT TIM1_SR1, #1, 0xB6
00003A 728F WFE
Event from timer has a probabilistic nature, and this code don't guarantee that it will happen after WFE instruction be executed:
I use manual PM0044, and at page 26 it content pretty table:
There 2 cases when code execution stalled at 3 cycles. So I'm not sure that my asynchronous wakeup event will not occur between BTJT and WFE instructions.
Is there ways to be ensure strict logical sequence (check condition > wfe > wakeup event)?
Solution found by OP:
I have read errata (thanks to Ross Ridge) few times more attentively, and this is main idea:
General solution is to ensure no interrupt request or event occurs during WFE instruction execution or re-execution cycle by proper application timing.