[SOLVED] Make always rebuilding dependencies

Make always rebuilding dependencies

When I use a Makefile without variable targets, things work fine

preamble:
        mkdir -p data
        touch $@

data/a: preamble
        touch $@

data/b: data/a
        touch $@

data/c: data/a
        touch $@

data/d: data/b data/c
        touch $@

diamond: data/a data/b data/c data/d
        touch $@

.PHONY: clean
clean:
        rm -rf ${data} diamond preamble

However, when I introduce a target variable tasks involved are always run.

data="data"
preamble:
        mkdir -p ${data}
        touch $@

${data}/a: preamble
        touch $@

${data}/b: data/a
        touch $@

${data}/c: data/a
        touch $@

${data}/d: data/b data/c
        touch $@

diamond: ${data}/a ${data}/b ${data}/c ${data}/d
        touch $@

.PHONY: clean
clean:
        rm -rf ${data} diamond preamble

These are always executed

touch "data"/a
touch "data"/b
touch "data"/c
touch "data"/d
touch diamond

What is the correct way to include variables in target?

Solution

I recommend not using quote marks. The Makefile does not need them, and they are confusing file names.

It is more common to say $(DATA) with parenthesis instead of ${DATA} curly braces.

Also, as a matter of practice, I recommend using variable names in all caps. Call it DATA instead of data.