Why there are 6 Base Address Registers (BARs) in PCIe endpoint?

After some reading about the PCIe, I came around the PCI compatible configuration headers and after understanding the header there is Base address Register(BAR) field. Where there are total 6 BARs in each PCIe endpoint. Why there are 6 BARs and not just 2 (1 in case 32 bit address and 2 in case 64 bit). I mean what is the detailed functionality of all the BARs?

Use of the BARs varies by device. They are used either for device control operations (this is the usual case) or for data transfer to/from the device. The reason there are six slots is to allow devices to provide different regions for different purposes. Also, since the interface supports 64-bit address spaces, providing one of those requires a 64-bit BAR (which requires two contiguous 32-bit slots) to configure the base address.

One example of the BAR usage can be seen in the datasheet for the Intel i350 Ethernet Controller. See section 9.4.11. There are 3 BARs in this device: one for memory-mapped device configuration (and access to a FLASH device), one for device configuration via I/O address space, and one for configuring MSI-X interrupt vectors.

Other devices may have one BAR or five (or none if the device is a bridge). If you're running linux, try sudo lspci -vv on your system to observe the variations among devices.