Realtionship between TLP packet and MMIO space
I'm trying to build a pci driver that can handle I/O traffic between cpu and custom fpga(xilinx) board. I built pci driver that can write and read into MMIO space, referring board's BAR address.
But what I'm confused with is, how actual board can access to the content written in MMIO space. Below figure is describing UltraScale+ Devices Block for PCIe ip :
In above figure, there is pcie_mgt, which describe physical PCIe ports. When user write or read on MMIO space, how data will be transferred throught these ports?
Also, as far as I know, PCIe traffic will be done by the form of TLP packets. When any traffic into MMIO space generated, how TLP packets will be generated?
As my knowledge is insufficient, this question may seem quite vague. Sorry in advance (_ _)
The accesses will be presented to you on the completer interface (m_axis_cq and s_axis_cc). You need to connect some logic to that to handle them as appropriate for your design. You can check PG213 for details.
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