What do the abbreviations (Rn, Rd, ...) in the instruction set of ARM mean?

Recently, I checked the Instruction Set for an ARM Cortex-M3 processor.
For example:

ADD <Rd>, <Rn>, <Rm>

What do those abbreviations mean exactly? I guess they mean different kinds of addresses, like directly addressed, relatively addressed or so. But what exactly?

Basics:

• Rd is the destination, Rn and Rm are sources. They're all general-purpose integer registers; FP would use Sd / Sn / Sm or Dd / Dn / Dm for single or double.
  ARM syntax puts the destination(s) on the left, before read-only source operands.

See Notlikethat's answer for more. Some small additions to that:

• t: in this post, an ARM employee comments that "t" might mean "transfer" instead of "target".

  Since t generally appears in memory instructions like LDR and STR, I understand that that means "transfer to/from memory", e.g. on ARMARMv8-fa:

  LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
  STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
  

  where the t is the source/destination of memory reads and writes.

  This is also further suggested in the description of the STR and LDXR instruction registers:

  <Xt> Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

  The LDR instruction however says "loaded":

  <Xt> Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

  This terminology is especially meaningful because ARM is RISC-y and so there are relatively few instructions that do memory IO, and they tend to do just that (unlike say add and store to memory as is common in x86).

• t1 and t2: these are used for memory instructions that load/store two values at once, e.g. the ARMv8 LDP/STP:

  LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
  STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
  

• n and m are just commonly used integer variable/index names in mathematics

• s:

  • the STXR instruction stores to memory fom Xt (like STR), but it also gets a second return value (did the write succeed) to Ws:

    STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]
    

    so presumably s was chosen because it comes before t like m comes before n.

  • Some ARMv7/aarch32 instructions could take a shift in a register, and Rs is the name given to that register, e.g.:

    ORR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> 
    

    I couldn't easily find aarch64 ones.

• if it were documented, "Chapter C2 About the A64 Instruction Descriptions" might have been a good location for the information, but it's not there