I'll try to be complete and specific:
NXP LPC1756 Cortex-M3. Eclipse Helios using Codesourcery ARM toolchain along with OpenOCD for debugging. JTAG is Olimex ARM-USB-OCD. OS is Windows 7 64-bit.
I believe I have the flash-upload side of things settled now. After programming I have the script perform a dump_image and the dumped image looks to be roughly correct. At the moment I have verification issues and need to sort that out but at this stage, it appears my JTAG setup is working and I am successfully communicating with the '1756.
However, when I try to debug I run into issues. First, my cfg files, starting with my target device cfg file:
# NXP LPC1756 Cortex-M3 with 256kB Flash and 32kB SRAM
debug_level 2
# LPC17xx chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
#source [find swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc1756
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CCLK ] } {
set _CCLK $CCLK
} else {
set _CCLK 4000
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
$_TARGETNAME configure -work-area-backup 0
#$_TARGETNAME configure -endian $_ENDIAN
#$_TARGETNAME configure -variant ARMv7
#delays on reset lines
adapter_nsrst_delay 200
jtag_ntrst_delay 200
#reset_config srst_only
#reset_config trst_and_srst srst_pulls_trst
# LPC1756 has 256kB of flash memory, managed by ROM code (including a
# boot loader which verifies the flash exception table's checksum).
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME \
lpc1700 $_CCLK calc_checksum
# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
jtag_khz 50
#$_TARGETNAME configure -event reset-init {
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
# and reside in flash instead).
#
# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
# Bit Symbol Value Description Reset
# value
# 0 MAP Memory map control. 0
# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
# 1 User mode. The on-chip Flash memory is mapped to address 0.
# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
#
# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
#MEMMAP - set user mode
# mww 0x400FC040 0x01
#}
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
#armv4_5 core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
#mwb 0xE01FC040 0x01
mwb 0x400FC040 0x01
#mwb 0xE000ED08 0x00
}
Now, my debug cfg file:
#define our ports
#telnet_port 4444
#gdb_port 3333
#commands specific to the Olimex ARM-USB-OCD
interface ft2232
ft2232_device_desc "Olimex OpenOCD JTAG A"
ft2232_layout "olimex-jtag"
ft2232_vid_pid 0x15BA 0x0003
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc1756
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
if { [info exists CCLK ] } {
set _CCLK $CCLK
} else {
set _CCLK 4000
}
if { [info exists ENDIAN ] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
debug_level 3
jtag_khz 100
#delays on reset lines
adapter_nsrst_delay 200
jtag_ntrst_delay 200
#reset_config srst_only
reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
#target cortex_m3 little 0 armv7
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
#
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
$_TARGETNAME configure -work-area-backup 0
#working_area 0 0x10000000 0x8000 nobackup
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x40000 0 0 $_TARGETNAME lpc1700 $_CCLK calc_checksum
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
#armv4_5 core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
mwb 0xE01FC040 0x01
mwb 0x400FC040 0x01
mwb 0xE000ED08 0x00
}
gdb_flash_program enable
init
#fast enable
jtag_khz 100
debug_level 1
In Eclipse, I invoke this tool with the flags:
-f arm-usb-ocd.cfg -f debug.cfg
This appears to work fine (at least I don't seem to get any errors in the console). Now comes the part where I have issues:
I have created a debug configuration in Eclipse (Run > Debug Configurations...) under GDB Hardware Debugging. Relevant parameters are:
Main:
C/C++ Application: output\project_UT1.elf
Debugger:
C:\CodeSourcery\bin\arm-none-eabi-gdb.exe
Startup:
Reset and Delay checked (2-seconds)
Halt checked
Initialization commands:
target remote localhost:3333
monitor flash device = LPC1756
monitor flash download = 1
monitor flash breakpoints = 1
monitor endian little
monitor speed 100
monitor speed auto
monitor reset halt
monitor writeu32 0x400FC040 = 0x00000001
monitor clrbp
Load image: not checked
Load symbols: checked
Runtime options: none of Set program counter, set breakpoint or resume checked
Run commands:
monitor reg sp = 0x10001ffc
monitor reg pc = 0x00001278
continue
Using "Standard GDB Hardware Debugging Launcher"
(NOTE: I've got the pc set to 0x00001278 as that was the address of my Reset_Handler; I know it should be 0x00000004 but I was experimenting; when it was 0x00000004 I got the same problems...)
When I attempt to debug using this set up I get a message saying "GDB Hardware Debugging Suspended", the PC appears to be at the bootloader 0x1FFF0080 and my debugger no longer seems to be connected. In the console I see stuff like:
.
.
.
target remote localhost:3333
0x1fff0080 in ?? ()
.
.
.
continue
Program received signal SIGINT, Interrupt.
0x1fff0080 in ?? ()
For example, in the disassembly window I can search for and find things like "main" or "Reset_Handler" but the disassembly is all "movs r0, r0" -- all zeros, basically. I can't single step (obviously, suspended...) Even at 0x1fff0080 it's displaying ""movs r0, r0". I do seem to be able to read the CPU registers (e.g. the sp shows 0x10001ffc and the pc shows 0x1fff0081 so maybe the JTAG interface isn't dead...)
My flashed image is supposed to be at 0x00000000 (i.e. the vector table there). When I do a dump_image, it appears the device is programmed and the vector table entries look right. Code protection? If so, how can I do an apparently successful "dump+image"?
However, even plugging the device in without the JTAG connected results in no operation. I've seen posts similar to this for the LPC1768 but haven't found anything that works for me. Any advice or suggestions greatly appreciated.
The reset-inithandler in your debug.cfg does too many useless mwb instructions. You should only do the mwb 0x400FC40 1 as this will remap the vector table at 0x0000 from ROM to Flash.
In your debugger config, you do monitor reset halt - change that to monitor reset init.
Then it reads Load image: not checked: Did you really forget to enable loading? That wolud cause gdb to not load your image to flash.