How to implement nand2tetris processor on a real FPGA?

I followed the nand2tetris course (https://www.nand2tetris.org/course) with the main intent to learn how to build a soft processor on a real FPGA.

While the course was simple enough, now that I am starting with the FPGA implementation I feel a bit lost.

I bought an Intel de10 nano FPGA(http://de10-nano.terasic.com/), and, having some Verilog knowledge from Uni, I was able to download "Quartus Prime Lite" and bootstrap with simple things like led blinking, etc...

However, when it comes to implement the processor there are several things that are not clear to me:

• How do I implement data memory? I saw there is a DDR3 module attached to the HPS of the FPGA. Is this something I need to directly use? Could I simply use a big 16bit register vector in HDL?
• How do I implement the ROM from where the program is read? And how can I store the binary I assembled to then bootstrap the fetch-decode-execute loop?
• How do I implement the screen and the keyboard? Indeed, there is also an HDMI controller on the board: do I have to implement all the logic myself?

Those are the main questions I am struggling with at the moment. Could you point me out to any resource useful for a complete novice?

Thanks,

For something as simple as a CPU from nand2tetris you'll be just ok with block RAMs, there's plenty of it on DE10Nano, likely enough for all your needs. Plus some more distributed memory.

In case if you still want an access to DDR, DE10Nano is an SoC, with a hard DDR controller managed by the processor subsystem. It's very easy to interface with it over an Avalon bus (don't bother with AXI unless you really need maximum possible performance).

For the ROM, just use LUTs. A simple static case in Verilog will be translated into an efficient LUT-based ROM.

For accessing HDMI on DE10Nano, you can take a look at this example: https://github.com/combinatorylogic/soc/blob/a1d282d793548030cba940496bed90ff3a29c0ba/backends/c2/hw/de10nano/vga1080p.v (you can also take a look at the DDR access in the same project). Before you can use HDMI you'll need to set up the ADV7513 chip over i2c, see a copy of a library from Terasic under the same project.

For a monochrome 800x600 video you'll be ok with a block RAM. For higher resolutions, as in the example above, you'll have to use DDR.