In RISC-V, new CSRs are planning to be added. This is the documentation on Github Page. It is addressed to two problems below.
• It introduces unpredictable noise to the counter values observed by the user.
• It leaks information about privileged software execution to user mode.
However, why there are no separate counters for different privilege modes to prevent leakage and noise? Adding mask registers will increase the complexity in hardware and address space in the CSR address part of instruction.
If you do want user+supervisor counts, you'd then have to read two different counters, which would happen at different times. That would put extra measurement overhead into the hot path while sampling, instead of just during setup. It would also mean more hardware counter state.
Plus, the samples wouldn't happen at exactly the same time, unless there was a way to atomically read two counters at once, which would probably require a new instruction and more logic. If an interrupt after reading the first, before reading the second, led to a context switch that ran more user + kernel code, the counts would be out of sync for this task.
Also, this model (masking to count user, supervisor, or both) is how performance counters work on some other ISAs, for example x86. So software like Linux perf is already set up to deal with that model, rather than with pairs of counters that both need to be read.