8086 is a 16bit microprocessor with a 20 bit address bus, this means that it can access upto 2^20 bytes of data. So my question is that if the memory is stored outside the microprocessor, thus the location say 1000H (starting address) is outside 8086, but the address 1000 is stored as offset in the registers in 8086, also if this is the case, then how does the segmentation in 8086 work, does it read the external memory in a segmented manner, or is the external memory actually segmented?
The logical seg:off to 20-bit linear address calculation (base + offset, where base = seg<<4) happens inside the 8086. The external physical address bus signals are linear, so it only has to be 20 bits wide, not 32!
See https://thestarman.pcministry.com/asm/debug/Segments.html for more discussion about segmented addressing and how different logical addresses can overlap the same linear address.
Address decoding outside the CPU is normally arranged with DRAM responding to the lowest addresses, ROM at the top, and memory-mapped I/O devices (such as a VGA card's video RAM) in between.
I/O addresses (IO "port" numbers for in / out instructions) use the same address lines in 8086, but it's a separate address-space entirely: there's an extra signal line that indicates whether the address on the bus is an I/O or memory address.
Unlike modern CPUs where IO accesses are routed to PCIe or internal devices instead of memory controllers, only going over the same busses as memory accesses inside the CPU's interconnect between cores, memory controllers, and system agent = link to chipset and PCIe busses. (Except PCIe MMIO accesses also go over the same PCIe external busses as PCIe IO-space accesses. Physical address space includes DRAM but also other stuff, such as ROM and device memory, which isn't accessed via the memory controllers built-in to modern CPUs. So the CPU has to internally route memory loads/stores according to their address. See https://superuser.com/questions/1226197/x86-address-space-controller/1226198#1226198)