I have a CVA6 design implemented to FPGA, I have connected the OpenOCD and after writing the image to RAM, I tried to verify it. But the verification fails and I get this message
verify_image uImage 0x80200000
Algorithm timed out after 180001 ms.
ra = 0x0
sp = 0x0
gp = 0x0
tp = 0x0
t0 = 0x0
t1 = 0x0
t2 = 0x0
s0 = 0x0
s1 = 0x0
a0 = 0x80200000
a1 = 0x82cb3e
a2 = 0x0
a3 = 0x0
a4 = 0x0
a5 = 0x0
a6 = 0x0
a7 = 0x0
s2 = 0x0
s3 = 0x0
s4 = 0x0
s5 = 0x0
s6 = 0x0
s7 = 0x0
s8 = 0x0
s9 = 0x0
s10 = 0x0
s11 = 0x0
t3 = 0x0
t4 = 0x0
t5 = 0x0
t6 = 0x0
pc = 0x80200040
mstatus = 0xa00001800
mepc = 0x80200040
mcause = 0xc
error executing RISC-V CRC algorithm
verified 8571710 bytes in 283.027466s (29.576 KiB/s)
The PC stucks at 0x80200040 address, the entry point and load address are 0x80200000, mcause = 0xc means Instruction page fault, but sometimes it shows mcause = 0x2 (Illegal instruction). Also I dump the 0x80200000 area and use objdump to see if there is some valid code there and I got this
Disassembly of section .data:
0000000000000000 <.data>:
0: 56190527 0x56190527
4: f842 fsw fa6,48(sp)
6: f7a1 bnez a5,0xffffffffffffff4e
8: 0765 addi a4,a4,25
a: 98003957 0x98003957
e: c1ad beqz a1,0x70
10: 2080 fld fs0,0(s1)
12: 0000 unimp
14: 2080 fld fs0,0(s1)
16: 0000 unimp
18: d4c1 beqz s1,0xffffffffffffffa0
1a: 07ca slli a5,a5,0x12
1c: 1a05 addi s4,s4,-31
1e: 0102 c.slli64 sp
20: 34365643 0x34365643
24: 3641 jal 0xfffffffffffffba4
26: 694c flw fa1,20(a0)
28: 756e flw fa0,248(sp)
2a: 0078 addi a4,sp,12
...
40: 8b1f 0808 5738 0x573808088b1f
46: 03026507 0x3026507
4a: 6d49 lui s10,0x12
4c: 6761 lui a4,0x18
4e: 0065 c.nop 25
50: 59ec lw a1,116(a1)
52: d713547b 0xd713547b
56: dfba sw a4,252(sp)
As you can see at 0x40 it doesn't look like instruction. Why does this happen?
I tried to verify the image with verify_image uImage 0x80200000. It was not verified, and this is strange because I used cva6-sdk to produce the image.
Actually this was due to wrong base address in openOCD config file. So I managed to fix it.