I have a FPGA DSP module that detect the pulse based on the threshold of the noise floor level. My module run the incoming IQ signal to a Xilinx CORDIC-Vector Translate module to produce phase and magnitude. The magnitude is compared to a NOISE_FLOOR_THRESHOLD to determine if it is a pulse. My question is, how can i calculate the noise floor level in FPGA? I read something about applying FFT to calculate the Power Spectrum Density (PDS), and then find the frequency bins that is associated with the noise (usually the lowest frequency bin. But I am not very clear on such algorithm. Any advice is greatly appreciated!
If you need to use the FFT to estimate the noise level, you should take one bin from the FFT where you are sure that there is only noise, integrate I^2+Q^2 over the full bandwidth of your signals (multiply by bins number),the hypothesis here is that your noise is uniformly distributed in frequency like the taken bin, what you get is an estimation of the noise variance. Translate in level (sqrt) and you have the std-deviation of noise in your signal. To have better estimation accuracy you should also window your signals, but then more details need to be adjusted.