What bytes do you receive back from the accelerometer? The I2C bus

image

C code snippet:

unit32_t I2C_BASE = 0x40001200UL;
int main(void)
{
    unit8_t accel_addr = 0xC9
    unit8_t recv_buf[2];
    I2C_MasterTransfer(accel_addr, recv_buf, I2C_BASE);
    return 0;
}

The image above shows I2C bus traffic (presumably from an oscilloscope) resulting from running the C code snippet.

The code addresses an accelerometer connected to an I2C bus:

• There are two physical lines: a clock line, SCL, and a data/address line, SDA.
• Transactions are initiated by the master pulling SDA low while the clock is high.
• The clock, SCL, is driven by the master, and bits are clocked on the rising edge.
• The first byte on SDA always represents the address and is driven by the master.
• The last bit in the first byte on SDA indicates whether it is a read transaction (1, high) or a write transaction (0, low).
• Every 9th bit is an ACK bit, given by either the slave (during reading) or the master (during writing).
• MSB comes first.

What bytes do you receive back from the accelerometer?

This is a taks i was given which i dont understand. The solution is given by my professor is: 0x64,0x5B/0x1B, 0xEC -- very tiring to read values ​​on screen. Spatially censored.

I dont understand the task at all and my exam is right around the corner. I cant understand anything out of my professors solution and dont know what to search for on the internet.

To post this is my last way to maybe understand this task. Any answer is appreciated. Thanks in advance! :)

I do now understand. Thanks to Attie at Stack Exchange. :)

"I've very roughly annotated the trace here, and I think your professor's solution is wrong (they're one bit out for the middle byte) 🙃 ... this trace is a bad example to try and learn from - the rising edge of the clock should be in the middle-ish of the SDA stable period... it's actually directly lined up with a transition on SDA in one place and very close in others. Very unlikely that this is based on a real-world trace, and if it is, then the bus / implementation / devices have "issues" that need to be resolved." – Attie Nov 23 at 13:04

Source question: https://superuser.com/questions/1817845/how-does-the-i2c-bus-traffic-work